Structures such as polycrystalline silicon (polysilicon) plugs, interconnects, and transistor gates are commonly formed during the manufacture of semiconductor devices such as microprocessors, memory devices, and logic devices. To manufacture a plug, for example, a masked dielectric layer is formed over an underlying substrate assembly and an etch is completed to form a hole in the dielectric which exposes the underlying structure in the area where contact is to be made. A blanket polysilicon layer is deposited over the dielectric layer which fills the hole in the dielectric layer and contacts the underlying structure. The polysilicon is then removed from a planar surface of the dielectric, typically using mechanical polishing such as a chemical mechanical polishing (CMP) process which leaves the plug formed within the dielectric layer. Interconnects and gates are typically formed by depositing a blanket layer of polysilicon over a semiconductor substrate assembly, then masking and etching the layer.
As the sizes of the plugs and line widths decrease with improved manufacturing technology, the doped polysilicon structure may provide insufficient conductance and excessive resistance. To reduce the resistance of a structure, a silicide layer is often formed underneath the plug or over the top of the plug, gate or interconnect. To form the silicide layer to enhance plug conductivity the silicide layer can be formed before formation of the plug. A titanium chemical vapor deposition (CVD) process results in titanium reacting with the exposed silicon wafer to form titanium silicide. An unreacted titanium metal layer will also form over any exposed dielectric layer which is then stripped. After stripping the unreacted titanium, the polysilicon plugs are formed over the silicide layer as described above.
A silicide layer can also be formed over the plug, transistor gate or other interconnect after forming the blanket polysilicon layer which forms the gate or interconnect. During a titanium CVD process similar to that described above for forming silicide under the plug, the titanium reacts with the polysilicon to form silicide on top of the polysilicon layer, then the polysilicon is masked and etched to define the line or plug.
While the silicide layer interposed between the silicon wafer and the polysilicon plug provides decreased resistance and increased conductance, it can also provide a path for leakage between an adjacent transistor channel region and an active area, thereby increasing junction leakage.
The following U.S. Patents, each assigned to Micron Technology, Inc. and incorporated herein by reference as if set forth in their entirety, describe various processes for forming silicide layers: U.S. Pat. No. 5,381,302 by Sandhu et al.; U.S. Pat. No. 5,198,384 by Dennison; U.S. Pat. No. 6,074, 960 by Lee, et al.; U.S. Pat. No. 6,194,315 by Hu, et al.; and U.S. Pat. No. 6,486,060 by Hermes, et al.
In particular, U.S. Pat. No. 6,486,060 discloses a process for forming a self-aligned titanium silicide layer over a plurality of polysilicon features, including conductive plugs and transistor gates (word lines). While the titanium silicide layer itself is self-aligned, a patterned dielectric layer which defines the subsequently-formed titanium silicide layer over transistor gates is not self-aligned to the locations on which the titanium silicide is to be formed. As feature sizes decrease, it becomes increasingly desirable to provide structures which are completely self-aligned with other structures where possible to decrease product loss which may result from misaligned mask layers and to decrease other costs associated with providing patterned masks. Further, titanium silicide becomes more difficult to scale as feature sizes decrease.
A process and structure which provides improved conductance and reduced resistance and which does not increase junction leakage would be desirable. It would be further useful to provide a plug having a maximized amount of silicide formed thereon. Additionally, it would be advantageous to have a process with which the silicide, as well as any layers required to form the silicide, is self-aligned to various polysilicon features and scaleable with decreasing features sizes.